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document number: mc33099 rev. 6.0, 1/2007 freescale semiconductor technical data ? freescale semiconductor, in c., 2007. all rights reserved. adaptive alternator voltage regulator the 33099 is designed to regulate the output voltage in diode- rectified alternator charging systems common to automotive applications. the 33099 provides either an analog or digital fixed frequency duty cycle (on/ off ratio) control of an alternator?s field current. load response control (lrc) of the alternator field current is accomplished by selecting the duty cycle for prevailing engine conditions to eliminate engine s peed hunting and vibrations caused by abrupt torque loading of the engine owing to sudden electrical loads being applied to the system at low engine rpm. four lrc rates are selectable by connecting pins 7 and 8 to ground. the 33099 uses a feedback voltage to establish an alternator field current that is in harmony with s ystem load currents. the output voltage is monitored by an internal voltage divider scheme and compared to an internal voltage ramp referenced to a bandgap voltage. this approach provides pr ecision output voltage control over a wide range of temperature, el ectrical loads, and engine rpm. features ? external high-side mosfet co ntrol of a ground-referenced field winding ? lrc active during initial start ?v set at 0.1 v @ 25c ? <0.1 v variation over engine speeds of 2,000 to 10,000 rpm ? <0.2 v variation over 10% to 95% of maximum field current ? controlled mosfet and field flyback diode recovery characteristics for minimum rfi ? trimmed devices available at 14.6 v and 14.8 v (typical) v set ? pb-free packaging designated by suffix code eg figure 1. 33099 simplified application diagram voltage regulator dw suffix eg suffix (pb-free) 98asb42567b 16-pin soicw 33099 ordering information device temperature range (t a ) package mc33099dw/r2 -40c to 125c 16 soicw mc33099cdw/r2 mcz33099eg/r2 16 soicw (pb-free) mcz33099ceg/r2 33099 field winding ignition switch chassis phase gate source phase filter bat ign lamp drain agnd lrc1 lrc2 remote gnd
analog integrated circuit device data 2 freescale semiconductor 33099 figure 2. 33099 simplifi ed internal block diagram figure . field mtb36n06e ignition 500 stator mr850 ground battery low pass 0.6 v over voltage detect 1.25 v bandgap reference regulator v dd internal v reg and bias current charge pump regulator min duty cycle or1 ld ov remote local sense phase batt gate v v ref (5.0 v) (2.0 v) 1.25 v s1 s2 cb1 cb2 lb fb css z1 v tssc a n d 4 s3 v g r1 r2 r3 r4 r5 rf cf v o uv ign delay gate polling local 4 lsb 4msb 8-bit counter digital duty cycle generator u/d counter np control switch up/down mux 1.25 v f2 dac a n d 3 1.25v batt polling drain lamp driver circuit or2 a n d 1 lcr1 lrc2 agnd gnd lamp drain lamp gate ign cds dtl z2 rs to logic polling lamp a n d 2 u/d u/d f1 a/d comparator & tracking limit current limit thermal batt dd v tigm i ign v tdsc f msb (otc) f msb osc remote phase alternate s tator configuration lcr test p 16 p 256 source phase filter cf boundry for ic mc33099 l pd l pu v rem v rs v ls c ph v l c rs v hvl v dac c dc c uv v fb c ign vbat
analog integrated circuit device data freescale semiconductor 3 33099 pin connections pin connections figure 3. 33099 pin connections table 1. pin function description pin number pin name formal name definition 1 gate gate drive controls the gate of the mosfet to control the alternator field current. 2 bat battery primary power connection to the system battery. 3 gnd ground source lamp current and digital ground. 4 lamp drain lamp drain controls the fault lamp current. 5 lamp gate lamp gate controls the fault lamp internal driver as an override function. 6 ign ignition controls the on or off function of the regulator. 7 8 lrc2 lrc1 load response control 2 load response control 1 inputs for selecting the lrc rate. 9 agnd analog ground ground connection for analog circuitry. 10 remote remote provides for external kelvin connection to system battery. 11, 14 nc no connect no internal connection to this pin. 12 lrc test load response control test provides acceleration of lrc rate for testing. 13 phase filter phase filter provides access to phase resistive divider for external phase filter capacitance. 15 phase phase sense input input for phase voltage. 16 source source coupled to source of mosfet to provi de a gate voltage reference and to monitor for source shorts to ground. gate gnd lamp drain lamp gate ignition lrc2 lrc1 bat source phase nc phase filter lrc test nc remote agnd 2 3 4 5 6 7 8 16 14 13 12 11 10 15 9 1
analog integrated circuit device data 4 freescale semiconductor 33099 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise not ed. exceeding these ratings may cause a malfunction or permanent damage to the device. rating symbol value unit electrical ratings power supply voltage load dump transient voltage (1) negative voltage (2) v bat +v max -v min 24 40 -2.5 v esd voltage human body model (3) machine model (3) (4) v esd1 v esd2 2000 200 v thermal ratings operating junction temperature t j 150 c operating ambient temperature range t a - 40 to 125 c storage temperature range t stg - 45 to 150 c power dissipation and thermal characteristics maximum power dissipation @ t a = 125c thermal resistance, junction-to-ambient p d r ja 640 85 mw c/w peak package reflow temperature during reflow (5) , (6) t pprt note 6 c notes 1. 125 ns wide square wave pulse. 2. maximum time = 2 minutes. 3. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). esd2 testing is performed in accordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 4. esd2 voltage capability of phase filter pin is greater than 150 v. all other device pins are as indicated. 5. pin soldering temperature limit is for 10 seconds maximum duration. not designed for immersi on soldering. exceeding these lim its may cause malfunction or permanent damage to the device. 6. freescale?s package reflow capability meets pb-free require ments for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), an d review parametrics.
analog integrated circuit device data freescale semiconductor 5 33099 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electri cal characteristics characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit regulation voltage @ 50% duty cycle v rem = v set or v rem < v trem mc33099 v rem = v set or v rem < v trem mc33099c v set 14.55 14.3 14.8 14.6 15.05 14.85 v regulation voltage range 10% < dc < 95% dvset ? 210 300 mv regulation voltage temperature coefficient (tc) v rem = v bat or v rem < v trem tc (v set ) -13 -11 -9 mv/c power up/down ign threshold voltage v tign 0.9 1.25 1.6 v operating drain current (ignition on) v ign > v tign , v rem = v ph = v set , t a = 25c v ign > v tign , v rem = v ph = v set , -40c t a 125c i q1(on) i q2(on) ? ? 6.5 6.5 8.0 8.4 ma standby drain current (ignition off) v ign < v tign , v ph = 0 v, v rem = v bat = 12.6 v, t a = 25c v ign < v tign , v ph = 0 v, v rem = v bat = 12.6 v, -40c t a 125c i q1(off) i q2(off) ? ? 0.6 1.0 1.5 3.4 ma remote loss voltage threshold v trem 4.2 4.5 4.8 v phase detection threshold voltage v tph 3.75 4.0 4.25 v undervoltage threshold voltage v set = 14.8 typical mc33099 v set = 14.6 typical mc33099c v tuv 10.9 10.35 11.35 10.95 11.6 11.55 v overvoltage threshold voltage v set = 14.8 typical mc33099 v set = 14.6 typical mc33099c v tov 16.15 15.8 16.65 16.4 17.15 17.0 v overvoltage threshold voltage tc tc(v tov ) ? -12.4 ? mv/c load dump threshold voltage v set = 14.8 typical mc33099 v set = 14.6 typical mc33099c v tld 18.9 18.45 19.25 19.15 19.8 19.85 v load dump threshold voltage tc tc(v tld ) ? -14.3 ? mv/c secondary regulation v set = 14.8 typical mc33099 v set = 14.6 typical mc33099c v set2 18.0 17.65 18.5 18.15 18.8 18.75 v secondary regulation tc tc(v set2 ) ? -13.4 ? mv/c secondary load dump threshold voltage v set = 14.8 typical mc33099 v set = 14.6 typical mc33099c v t ld2 23.5 23.5 24 23.85 25 24.65 v secondary load dump threshold voltage tc tc(v t ld2 ) ? -17.9 ? mv/c
analog integrated circuit device data 6 freescale semiconductor 33099 electrical characteristics static electrical characteristics lamp drain short circuit threshold voltage (7) v t dsc 1.8 2.25 2.85 v lamp drain short circuit current i dsc 2.0 2.5 3.0 amps lamp drain on voltage i lamp = 0.4 a v d(sat) ? 0.3 2.5 v lamp drain-to-gate clamping voltage v dg ? 48.48 55 v lamp gate override resistance r lg ? 4.6 ? k ? lamp driver thermal shutdown temperature limit (7) t lim ? 185 ? c gate drive source current i pu 240 300 340 a gate drive sink current i pd 400 480 560 a gate drive gate-to-source clamping voltage v gs 10 12 15 v minimum charge pump gate drive voltage v bat = v source = v set v g(min) 21.5 23.4 ? v source short circuit threshold voltage v tssc 1.85 2.3 2.75 v remote input resistance v rem = v set r rem ? 68 ? k ? phase input resistance v ph = v set r ph ? 60 ? k ? ign input pull-down current v ign = 1.25 v i ign 40 73 90 a lrc input current v lrc = 0 v i lrc 35 45 55 a notes 7. not 100% tested. table 3. static electrical characteristics (continued) characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 7 33099 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electrical characteristics characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit duty cycle regulation output frequency f osc / 256 f dc 300 375 440 hz phase rotation detection frequency f 1 44.28 49 53.8 hz low / high rpm transition phase frequency f 2 267.5 296 325 hz gate duty cycle at startup and wot f ph > f 2 dc start 30 31.25 34.5 % minimum gate lrc duty cycle f ph < f 2 dc (lrc)min 29 31.25 33.5 % minimum gate duty cycle v bat > v reg(max) dc min 2.1 3.1 3.3 % lrc increasing gate duty cycle rate low rpm mode (f ph < f 2) lrc1 at gnd, lrc2 at gnd lrc1 open, lrc2 at gnd lrc1 at gnd, lrc2 open lrc1 open, lrc2 open high rpm mode (f ph > f 2) r lrc1 r lrc2 r lrc3 r lrc4 r lrc (max) ? ? ? ? ? 9.31 12.45 18.71 37.42 616 ? ? ? ? ? %/s ignition turn off delay (lamp on) t id (off) ? 10.2 ? ms lamp short circuit on polling frequency f lsc ? 98.6 ? hz lamp short circuit on duty cycle dc l ? 1.56 ? % lamp off polling frequency f l (off) ? 98.6 ? hz lamp polling off duty cycle dc l (off) ? 1.56 ? % field short circuit on polling frequency f fsc ? 98.6 ? hz field short circuit po lling on duty cycle dc f ? 1.56 ? %
analog integrated circuit device data 8 freescale semiconductor 33099 functional description introduction functional description introduction the 33099 is specifically designed for regulation of an automotive system voltage usin g diode-rectifi ed alternator charging systems commonly found in automotive applications. the 33099 provides either an analog or digital duty cycle control of an on/off ratio of an alternator field current at a fixed frequency. this provides for a load response control (lrc) of the alternator field current at low engine rpm to eliminate engine speed hunting and vibration owing to abrupt torque loading of the engine when a sudden electrical load is applied to the system. four lrc rates are selectable using a combination of pins 7 and 8 being connected to ground. the 33099 provides a regulated voltage feedback system to activate the alter nator field current in response to system load current. the output voltage is monitored by an internal voltage divider scheme and compared to an internal voltage ramp referenced to a bandgap voltage. the 33099 regulates the system voltage to 14.8 v for the dw suffix and to 14.6 v for the cdw suffix by generating a pulse width modulation (pwm) voltage waveform at the gate of an external mosfet to provide an average alternator field coil current as a function of the internal voltage comparison.
analog integrated circuit device data freescale semiconductor 9 33099 typical applications introduction typical applications introduction the 33099 is an alternator voltage regulator designed with internal level shifting resistors to control the voltage in a 12 v automotive system that uses a three-phase alternator with a rotating field winding. the system shown in figure 4 includes an alternator with its associated field coil, stator coils and rectifiers, an automo tive battery, a fault indicator lamp, an ignition switch, a field flyback diode, and the 33099. figure 4. 33099 simplified application the 12 v system voltage (v bat ) is connected to a remote input by a remote wire, which provides the ic regulator with an external kelvin connection directly to the battery to provide remote voltage, v rem . the system voltage at the bat pin is also sensed by an internal local ic connection as local voltage v l . the local connection is provided in the event the remo te wire or remote connection becomes faulty such as being resistive, an open, or shorted to ground. the phase input is normally connected to a tap on one corner of the alternator's st ator winding, which provides an ac phase voltage (v ph ) for the ic to determine the rotational frequency (f ph ) of the alternator rotor. two frequency comparators (f1 and f2) monitor voltage v ph to determine a phase rotation detection frequency (f 1 ) and a low/ high rpm transition phase frequency (f 2 ), respectively. a phase filter pin is provided for externally providing a filter capacitance for filtering phase input noise. the regulated dc system set voltage (v set ) is achieved by employing feedback to compare a ratioed value of v set to an internal ic bandgap voltage reference having a negative temperature coefficient (tc). the gate drive of an external n-channel mosfet is regulated by the ic to control the field current in the alternator field coil as an alternating on or off state dependent on load current conditions affecting voltage v set . the external mosfet receives gate-to-source voltage drive from between t he gate and source output pins of the ic. the gate-to-source voltage is a pulse width low pass 0.6 v over voltage detector 1.25 v bandgap reference regulator regulator v dd internal v reg and bias current regulator charge pump regulator min duty cycle generator or1 ld ov remote local sense phase batt gate source v v (5.0 v) (2.0 v) 1.25 v s1 s2 cb1 cb2 lb fb css z1 v tssc a n d 4 s3 v g r1 r2 r3 r4 r5 rf cf vls v o vl uv ign delay circuit gate polling circuit local 4 lsb 4 msb 8-bit counter digital duty cycle generator u/d counter np control switch up/down mux 1.25 v f2 dac a n d 3 1.25v battery polling lamp driver circuit or2 a n d 1 lcr1 lrc2 agnd gnd lamp drain lamp gate ign dtl z2 rs to logic a n d 2 u/d u/d drain f1 a/d duty cycle comparator & tracking circuit limit current detector limit thermal detector battery ref dd v tigm i ign v tds c (otc) osc 101 khz lcr test p 16 p 256 phase filter 1 2 10 11 circuit lamp polling circuit v rem v rs c ph c rs v hvl v fb c dc c uv c ign c ds l pd l pu v dac
analog integrated circuit device data 10 freescale semiconductor 33099 typical applications modulated (pwm) waveform having a variable on / off duty cycle ratio that is determined by an analog or a digital duty cycle control circuitry that re sponds to variations in the system voltage due to variations in system load current. the pwm waveform has a duty cycle regulation output frequency of about 395 hz (f dc ) defined by an 8-bit division of an internal 101 khz oscillator clock frequency (f osc ). the gate voltage at the gate pin is due to a charge pump gate voltage (v g ) generated by voltage multiplication using an internal charge pump voltage regulator. the high gate-to-source voltage applied to the external mosfet during the on cycle of the pwm waveform minimizes a low drain-to-source on resistance (r ds(on) ) and associated drain-to-source voltage v d(sat) to maximize the field current while minimizing the associated power dissipation in the mosfet. a unique feature of the 33099 is the combinational use of analog and digi tal duty cycle controllers to provide a load response control (lrc) duty cycle function when rotor frequency f ph is less than frequency f 2 . a classic analog duty cycle function is provided at the gate output when frequency f ph is greater than frequency f 2 . during the lrc mode when f 1 < f ph < f 2 , a sudden decrease in the system voltage due to a sudden increase in system load current will cause the analog duty cycle to rapidly increase to as great as 100%. however, the lrc circuitry causes the digital duty cycle to increase to 100% at a controlled predetermined lrc rate and overrides t he analog duty cycle. thus the alternator response time is decreased in the lrc mode and prevents the alternator from placing a sudden high torque load on the automobile engine during this slow rpm mode. this can occur when a high current accessory is switched on to the 12 v system, producing a sudden dr op in system voltage. when frequency f ph is greater than frequency f 2 , the slow lrc response is not in effect and the analog duty cycle controller controls the pwm voltage wavefo rm applied to the external mosfet to regulate the system voltage. by selectively coupling the lrc1 and lrc2 pins to ground or leaving them open, the user can program four different lrc rates (r lrc1 - r lrc4 ) from 9.37%/sec to 37.4%/sec. during an initial ignition on and engine start-up, the lrc rate is also in effect to minimize alternator torque loading on the engine during start, even when a wide open throttle (wot) condition (f ph > f 2 ) occurs. an internal n-channel mosfet is provided on the ic to directly drive lamp current as a fault indicator. the fault lamp is connected between the low side of the ignition switch and the lamp drain pin of the ic. a fault is indicated during an undervoltage battery condition when frequency f ph is greater than frequency f 2 , during an overvoltage battery condition, and when frequency f ph is less than frequency f 1 . frequency f ph < f 1 when an insufficient altern ator output voltage results or a slow or non-rotating rotor occurs due to a slipping or broken belt. an external lamp gate pin is also provided for the internal lamp driver to a llow the user to override the internal ic fault logic and externally drive the internal lamp drive mosfet. when a loose wire or battery pin corrosion causes the remote voltage to decrease but is not a remote open condition, the system volt age will increase, causing an overvoltage lamp fault indication, and is regulated at a secondary value of about 18.5 v. during a system load dump condition, load dump protection circuitry prevents gate-to-source drive to the external mosfet and to the internal lamp drive mosfet. this ensures that neither the field current nor the lamp current is activated during load dump conditions. a drain-to- gate voltage clamp is also provided for the internal lamp driver for further protection of this driver during load dump. an ignition pin (ign) is provided to activate the regulator from the standby mode into a normal operating mode when the ignition switch is on and an ignition voltage (v ign ) is greater than a power up/down ignition threshold voltage (v tign ). when the ignition switch is off, voltage v ign is less than voltage v tign , and the regulator is switched into a low current standby mode, when frequency f ph < f 1 . the ign pin can either be coupled to the low side of the ignition switch or to the low side of the lamp. when the ign pin is connected to the low side of the lamp, t he lamp must be shunted by a resistor to ensure that ignition on is sensed, even with an open lamp fault condition. when the lamp in on, lamp current is polled off periodically at an ignition polling frequency in order for the ign pin to periodically sense that the ignition voltage is high even though the lamp is on. an ignition input pull-down current (i ign ) is provided to pull voltage v ign to ground when the ign pin is open or terminated on a high resistance. two ground pins are provi ded by the 33099 to separate sensitive analog circuit ground (agnd) from noisy digital and high-current ground (gnd). alternator regulator biasing and power up/down the biasing of the regulator is derived from the bat pin voltage v bat . in the normal operating mode when the ignition switch is on and voltage v ign is greater than v tign (about 1.25 v), a 5.0 v v dd voltage regulator biases the ic logic and provides bias to a bandgap shunt voltage regulator. the bandgap regulator maintains a reference voltage (v ref ) of approximately 2.0 v with an internal negative temperature coefficient (-tc) as well as a 1.25 v zero temperature coefficient (otc) reference voltage. additional bias currents and reference voltages, including a charge pump gate voltage v g , are also generated from voltage v bat . the typically ignition on drain current (i q1(on) ) is about 6.5 ma at 25c. when the ignition switch is off and voltage v ign is less than v tign , the regulator is in a low current standby mode, having a standby drain current of about 0.7 ma (i q1(off) ) at 25c. during the sleep mode, some internal voltage regulators and bias curr ents are either terminated or minimized. however, the v dd regulator and the bandgap voltage regulator continue to maintain voltages v dd for the logic, the 2.0 v v ref , and the 1.25 v reference voltage. in addition, all logic is reset in the standby mode. after switching the ignition switch to the on position, voltage v ign will exceed voltage v tign , causing comparator c ign to switch states, providing an ignition-on signal to the ignition delay circuit. after an ignition start delay time of 500 ms, the ignition delay circuit activates additional current
analog integrated circuit device data freescale semiconductor 11 33099 typical applications for the v dd regulator and activates all other voltage regulators and bias currents. after engine start, the lrc mode is activated, independent of the phase frequency or independent of a wide open throttle condition. when the battery system volta ge increases to v set , the regulator resumes the normal operational mode. after switching the ignition switch to the off position, voltage v ign decreases below voltage v tign , causing the comparator c ign to provide an ignition-off signal to the ignition delay circuit. after phase frequency f ph < f 1 due to ignition turn off, supply currents and voltages are reduced in the regulator to provide the standby drain current drain. however, voltage v dd for logic and voltage v ref for reference voltages remain active to be able to sense an ignition input voltage. in some applications, the igni tion input is connected to the low side of the fault lamp as shown in figure 4 , page 9 . when the lamp driver circuitry is generating a lamp on signal, a lamp polling signal causes the lamp drain output to be periodically gated off. as a result, voltage v ign > v tign during the lamp off polling period, causing comparator c ign to periodically provides an ignition-on signal to the ignition delay circuit. during the lamp on condition, the ignition delay circuit provides a minimum ignition turn-off delay (t id(off) ) such that all currents and regulator voltages remain on between the lamp off polling pulses. battery and alternator output voltage sensing the system battery voltage is directly sensed by the remote input using a remote wire as a kelvin connection. the remote input resistance (r rem ) at the remote input is typically 68 k ? . the voltage at the remote sense input (v rs ) is a ratioed value of the remote voltage (v rem ). the intended ratio of v rem / v rs is about 7.45. the bat pin voltage (v bat ) is also sensed as an internal local voltage (v l ). a local sense voltage (v ls ) is a ratioed value of voltage v l , where the intended ratio of v l / v ls is also 7.45. the local internal connection is provided for fault protection against the remote wire being grounded or exhibiting a high remote wire resistance due to being disconnected or due to a corrosive or loose connection. thus the local connection ensures that alternator regulation of the syst em voltage continues in well- defined states for all possible remote input fault conditions. local and remote voltage processing and switching during remote operation both the external remote input connection and internal local connection senses approximately the same regulated system voltage of v set = 14.8 v. for this case, voltages v rs and v ls are approximately 2.0 v. because the remote switching comparator c rs is referenced to 0.6 v, both switches s1 and s2 are open and remain open when voltage v rs > 0.6 v or when voltage v rem is greater than the remote loss threshold voltage (v trem ). voltage v rs is coupled to the input of a unity-gain combiner / buffer cb1. voltage v ls is buffered and coupled to the output of a unity-gain local buffer (lb) and ratioed by the r5 / (r4+r5) resistor divider to provide an input voltage to a unity- gain combiner / buffer cb2. thus the vo ltage at the input of the combiner cb2 is normally 0.8 v ls (or 1.6 v typically), while voltage v rs on the input of cb1 is typically 2.0 v. because voltage v o reflects the highest voltage at the input of either combiner, voltage v o will be voltage v rs in remote operation with remote connected to v bat . for this case, voltage v rs is filtered by a 300 hz low-pass filter and translated to the fb buffer output. voltage v rs at the fb buffer output is then compared to a digital-to-analog converter output voltage ramp (v dac ) for duty cycle regulation. during a remote fault condition when the remote sense line is open or grounded, voltage v rs at the remote sense input will be zero, causing comparator c rs to activate switches s1 and s2 to a closed position. as a result, voltage v ls is coupled through buffer lb directly to the input of combiner cb2. because the voltage v ls on the input of combiner cb2 is greater than voltage v rs (= 0 v) on the input of combiner cb1, voltage v ls is coupled to the output of the combiners as voltage v o . thus in this fault case, voltage v ls is filtered and translated to the fb buffer output for being compared to voltage ramp v dac for regulation. during a remote fault condition in which the resistance of the remote sense wire increases due to the corrosion or a loose connection, a finite external remote fault resistance occurs causing voltage v rem to decrease, but voltage v rem remains greater than voltage v trem . as a result, switches s1 and s2 remain in an open condition, while the system voltage will increase due to t he effective increase in the remote resistor divider ratio. as a result, voltage v l increases until the voltage at the input of combiner cb2 is approximately 2.0 v, or v ls is about 1.2 (2.0 v), or 2.25 v due to the r4 / r5 divider ratio. because the local divider ratio translates voltage v ls to v bat by about factor 7.4, the final regulated output voltage for this condition is 7.4 (2.25), or 18.5 v. this is the secondary regulation voltage (v set2 ). when the system voltage increases to the overvoltage threshold (v tov ), a fault indication occurs by the lamp. thus this particular remote fault condition produces a fault indication, but regu lates to prevent an extreme system overvoltage condition. when the remote fault resistance becomes great enough to cause voltage v rem < v trem , the regulated system voltage return s to the local regulation as described for an open or grounded remote input. internal clock oscillator and 8-bit counter an internal clock oscillator is provided having a typical oscillation frequency (f osc ) of 101 khz. the output of the oscillator is coupled to an 8-bit counter that provides 8 counting bits to the logic and the four most significant counting bits (msb) to the lrc circuitry and to a digital-to- analog converter (dac) waveform generator. the output msb frequency (f msb ) of the 8-bit divider is about 395 hz (f msb = f osc / 256), which determines the pwm frequency at the gate output. an external lrc test pin is provided for accelerating internal testing of the lrc function and logic. under normal operation, the lrc test pin is grounded by an internal 10 k ? resistance to ground. under accelerated test conditions, the lrc test voltage is 5.0 v, and a fourth bit (f osc /16) from the 8-bit divider is used to determine the
analog integrated circuit device data 12 freescale semiconductor 33099 typical applications pwm gate frequency. thus, the rates are accelerated by a factor of 16. low-pass filter, dac, and analog duty cycle regulator comparator the output voltage v o of combiners cb1 and cb2 is coupled to an input of a 300 hz low-pass filter (rf, cf) to remove high-frequency components of system noise at v bat and thus associated with voltages v ls , or v rs . the output of the low-pass filter is coupled to a unity-gain buffer fb that provides a filter buffer fb output. the 4 msbs of the 8-bit counter causes the dac to generate a 4-bit 395 hz voltage waveform having 16 descending 1.75 mv steps, ramping from v ref to [v ref - 28 mv], where v ref is the 2.0 v reference voltage. an analog duty cycl e comparator (c dc ) compares the dac output voltage waveform to the voltage at the fb output (v fb ). when voltage v fb is less then voltage [v ref - 28 mv], comparator c dc outputs a logic [1], for a 100% duty cycle. when voltage v fb is greater than v ref , comparator c dc outputs a logic [0] for a 0% duty cycle. when (v ref - 28 mv) < v fb < v ref , comparator c dc outputs a duty cycle defined by the high / low output voltage ratio for each period (about 2.54 ms) of the dac output voltage waveform. basic system voltage regulation from a system voltage regulati on viewpoint, the voltages v rem and v l from the remote or local connections, respectively, are scaled to the remote sense and local sense inputs as voltages v rs and v ls respectively and transferred to the fb output as voltage v fb . voltage v fb is compared to the dac output voltage waveform to generate the on and off time of t he analog duty cycle waveform. when voltage v fb is less than v ref - 28 mv, the output of comparator c dc is in a high state. th is high state propagates through an and3 gate, an or1 gate, and an and4 gate to activate switch s3, generating a fully on or high gate drive voltage. when voltage v fb is greater than v ref , the output of comparator c dc is in a low state. this low state propagates through the and3 gate, the or1 gate, and the and4 gate to activate switch s3 to generate a fully off or low gate drive voltage. assuming voltage v ref is 2.0 v and v fb = v rs , and the local or remote input resistive scale factor is 7.45, the external mosfet provides a fully on field current when the system vo ltage is less than 7.45 (v ref - 28 mv), or 14.6 v. the field current is also fully off when the system voltage is greater than 7.45 (v ref ), or 14.9 v. when voltage v fb is less than any portion of the dac waveform voltage, comparator c dc output is high to produce an on field current. when voltage v fb is greater than any portion of the dac wavefo rm voltage, comparator c dc output is low to produce an off fi eld current. thus the system feedback will regulate the pwm duty cycle of the field current from 0% to 100% over about a 210 mv system regulation voltage range (dvreg). the syst em voltage is centered at 14.8 v, where a 50% duty cycle field current results for an average system load current, and the duty cycle regulation frequency is (f osc / 256), or 395 hz. since voltage v ref has a negative tc, voltage v set will also have a regulation voltage temperature coefficient (tc vreg ) of about -11 mv/ c. input phase and frequency switch response the phase voltage v ph results from the alternator's stator ac output voltage being appl ied to the phase input pin. a phase detection threshold voltage (v tph ) is approximately 4.0 v due to the 1.25 v phase reference voltage for the phase comparator (c ph ) and the 3.22 voltage ratio associated with the phase input resistor divider. the phase input resistance (r ph ) is typically 60 k ? . a phase filter pin is coupled to the input of comparator c ph , providing for an external phase filter capacitance when filt ering of high frequency phase noise is desired. a typical value of .003 f to agnd provides for an input phase 3.0 db roll-off frequency of about 10 khz. comparator c ph also provides about 480 mv of hysteresis at the phase input pin. comparator c ph further provides a phase signal binary output voltage having a phase frequency of f ph and is applied to digital frequency switches f1 and f2. switch f1 outputs a logic [1] when frequency f ph is less then phase detection frequency f 1 . frequency f 1 is equal to frequency f msb / 8, or 49.3 hz for a 101 khz oscillator frequency. switch f2 outputs a logic [1] when the frequency f ph is greater then the low/high transition frequency f 2 . frequency f 2 is equal to frequency 3f msb /4, or 296 hz for a 101 khz oscillator frequency. th ese frequency switches are used to define the load response control region of operation, an undervoltage at a high rpm fault condition, and a low rpm fault condition due to a broken or loose belt. load response control (lrc) the lrc circuit consists of a digital duty cycle generator, an analog/digital (a/d) duty cycle comparator and tracking circuit, an up/down control s witch, an up/down (u/d) counter, a programmable divider (np), and a multiplexer (mux). during normal operation, the lrc circuit becomes active and generates digital duty cycle cont rol of the gate drive when frequency f ph is less than frequency f 2 (f 1 < f ph < f 2 ). the slow lrc response becomes inactive and the analog duty cycle controls the gate drive when frequency f ph is greater than frequency f 2 (f 1 < f ph < f 2 ). during initial ignition and initial engine start, the lrc response is in effect, independent of frequency f ph , until system voltage is regulating at voltage v set . the digital duty cycle generator receives the 4 msbs from the 8-bit counter as input a nd generates 11 discrete digital duty cycles on 11 output lines. the frequency of each duty cycle waveform is about 395 hz (f msb ), which results from the msb of the 8-bit division of the 101 khz osc clock frequency. the minimum duty cycl e on the first output line is 31.25% and the maximum duty cycle on the eleventh output line is 93.75%. the duty cycl e difference between each incremental duty cycle is 6.25%. all 11 duty cycle generator output lines are coupled as data inputs to the mux.
analog integrated circuit device data freescale semiconductor 13 33099 typical applications normally the programmable divider np divides frequency f msb by a counter divide ratio n and applies the f msb /n frequency as input to the u/d counter. divide ratio n can be pre-selected by the user for four different divide ratios by switching a combination of the lrc1 and lrc2 normally open pins to ground. an lrc input current (i lrc ) from each lrc pin to ground is about 45 a. the phase frequency f ph and an up/down (u/d) state on a u/d line from the up/down control switch determines ratio n. in the lrc mode when f ph < f 2 , a high, or up, state on the u/d line causes divider np to output a frequency of f msb /n, or 395 hz/n. the lrc1 and lrc2 pin combinations produce n divide ratios of 66, 132, 198, and 264. when the u/d line is in the down, or low, state, divider np provides a divide ratio of f msb /4, or 395 hz /4. when f ph > f 2 , the output frequency of divider np is always f msb /4 = 395 hz /4, independent of the state of the u/d input line. the u/d line from the up /down control switch determines the direction of the count as we ll as the divide ratio n. for an up state on the u/d line, the out put of the 4-bi t u/d counter increments up at a rate of 5.98 hz (count change every 167 ms) for n = 66, 2.99 hz (count change every 334 ms) for n = 132, 1.99 hz (count change every 502 ms) for n = 198, or 1.496 hz (count change every 671 ms) for n = 264. for a down state on the u/d line, the ou tput of the 4-bit u/d counter decrements at a rate of about 99 hz (count decrement about every 10 ms). the 4-bit output lines of the up / down counter are coupled as control inputs of the mux. the mux couples one of the 11 digital duty cycle input lines to the mux output d ependent upon the 4-bit control inputs from the u/d counter. when the mux control input count is 0, the firs t 31.25% digita l duty cycle is selected and provided at the mux output. when the control input count is 10, the eleventh 93.75% digi tal duty cycle is selected at output of the mux. a mux cont rol input of 11 produces a 100% duty cycle at the mux outp ut. thus each of the mux input lines is selected and provided at the mux output and incremented to the next line at a rate dependent on the rate the mux control inputs increment. for an up state on the u/d line, the digital duty cycle at the output of the mux will increment from 31.24% to 100% in 11 steps at a rate from 167 ms/step (or a fourth lrc rate (r lrc4 ) of 37.42% /sec) to 671 ms/step (or a first lrc rate (r lrc1 ) of 9.31%/sec) dependent on the lrc1 and lrc2 pin terminations. for a down state on the u/d line, the digital duty cycle will count down at a rate of about 10 ms/step change. the a/d duty cycle comparat or and tracking circuit receives the analog duty cycle from comparator c dc and the digital duty cycle from the mu x output. the a/d duty cycle comparator provides a high, or up (u), output when the analog duty cycle is great er than the digital duty cycle, and a low, or down (d), output when the analog duty cycle is less than the digital duty cycle. in the lrc mode when frequency f 1 < f ph < f 2 , the up / down control switch enables the u / d output of the a/d duty cycle comparator to be coupled to the u / d line. in the steady state, the a/d duty cycle co mparator will provide an u / d input to the u/d counter and np divi der to increase or decrease the digital duty cycle to track the analog duty cycle. if the analog duty cycle increases to a value greater than the digital duty cycle at a rate that is greater than the selected lrc digital duty cycle rate, the a/d duty cycl e comparator will output an up signal on the u/ d line to caus e the digital duty cycle to increase to the analog duty cycl e at the selected lrc digital duty cycle rate. if the analog duty cycle decreases to a value less than the digital duty cycle , the a/d duty cycle comparator will output a down signal on the u/d line to cause the digital duty cycle to decrease to the an alog duty cycle at a fixed rate of about 10 ms/step. for an analog duty cycle less than 31.25%, the down count at the output of the u/d counter will remain at 0 and the digital du ty cycle will remain at 31.25%. if frequency f ph is less than frequency f 1 (f ph < f 1 ), then the up/down control switch will provide a down signal on the u/d line independent of the duty cycl e comparator u/ d output. the resulting down count of 0 to the mux control input for f ph < f 1 will cause the digital duty cycle to be constant at 31.25% and provides a divide ratio of f msb /4 as the input frequency to the u/d counter. when approximately 5.0 v is applied to the lrc test pin, divider np utilizes the f osc /16 frequency as input to the divider instead of the normal f osc /256 frequency. as a result, the lrc function is accelerated by a factor of 16, which allows the testing of all lrc associated rates to be accelerated by a factor of 16. during normal lrc operation, the lrc pin is in a low ground state, having an internal 10 k ? pull-down resistor. the duty cycle output of the and3 gate reflects the minimum duty cycle at the and3 gate inputs. thus when the analog duty cycle exceeds the digital duty cycle, the digital duty cycle becomes the c ontrolling duty cycle at the and3 gate output. when the analog duty cycle is less than the digital duty cycle, the analog duty cycle becomes the controlling duty cycle at the a nd3 gate output. thus in the lrc mode when f 1 < f ph < f 2 , an increasing step response in the analog duty cycle from 0% to 100% will cause the duty cycle at the output of the and3 gate to increase rapidly from 0% to 31.25% and then increase slowly at the lrc rate from 31.25% to 100%. if the analog duty cycle provides a step increase from a duty cycle greater than 31.25%, then the resulting lrc duty cycle increase from the initia l analog duty cycle at the output of the and3 gate. for a decreasing step response in the analog duty cycl e, the output of the and3 gate will rapidly follow the decreasing analog duty cycle. the output of the and3 gate drives the gate output (and the field current) through an or1 gate, an and4 gate, and switch s3. thus the mi nimum gate lrc duty cycle (dc (lrc)min ) is 31.25%. a 0% analog duty cycle will prod uce a 0% duty cycle at the output of the and3 gate. however, the output of the and3 gate is ored with a 3.1% minimum duty cycle signal from the minimum duty cycl e generation at the or1 gate input to provide a minimum 3.1% duty cy cle to the and4 gate input. this provides the resulti ng minimum gate duty cycle (dc min ) of 3.1% at the gate ou tput, even though the analog duty cycle is 0%.
analog integrated circuit device data 14 freescale semiconductor 33099 typical applications when the phase frequency is greater than frequency f 2 (f ph > f 2 ), the n divide factor is reduced to 4. as a result, the lrc circuitry still functions as previously described, but the rate of digital duty cycle increase or decrease is a maximum lrc rate (r lrc(max) ) of about 10 ms/step. thus a step increase in the analog duty cycle from 31.25% to 100% will cause about a 110 ms delay before the digital duty cycle provides a 100% duty cycle at the output of t he and3 gate (and gate drive). the conditions for lrc response also occur during an initial engine start up period after engine cranking even when a wot condition occurs (f ph > f 2 ). when the ignition switch is turned on, comparator c ign is activated, activating all biasing into the normal state and activa ting the start-up lrc mode. after engine cranking and immediately after initial engine start up, the system battery vo ltage is generally low while a wot condition occurs. for this case, the slow lrc response is in effect to prevent excessive torque loading on the engine by the alternator during engine start up. the gate duty cycle at start-up with wot (dc start ) is the minimum lrc duty cycle and will increase at the lrc rate. once the system volta ge returns to voltage v set , the normal lrc response will occur as previously described. field coil drive and device protection the external mosfet provid es pwm drive current from the system battery to the field coil for system voltage regulation. the gate-to-source voltage for this mosfet is provided by the ic's gate-t o-source pin drive voltage. during the on state, the and4 gate activates switch s3 to couple the gate drive pull-up source current (i pu ) to the gate output. current i pu drives the gate of the mosfet to the charge pump gate voltage v g (typically 23 v), causing the mosfet to drive the field coil pin to near the system battery voltage. voltage v g has a minimum charge pump gate voltage (v g(min) ) of 21.5 v. this high gate-to-source voltage minimizes power dissipation in the external mosfet by minimizing a drain-to-source on resistance (r ds(on) ) of the mosfet during the on state. this results in a typical lamp drain on voltage (v d(sat) ) of about 0.3 v at a lamp drain current of 400 ma as measured from the lamp drain pin to ground. during the off state, the and4 gate activates switch s3 to couple a gate drive pull-down sink current (i pd ) to the gate output. current i pd pulls the gate voltage to the source voltage, turning off the mosfet and its associated field coil curr ent. the limited gate current drive of the mosfet gate capacitance reduces the magnitude and frequency of the high-frequency components associated with th e gate duty cycle waveform, minimizing rfi. zener diode z1 is employed to provide a gate-to- source clamping voltage (v gs ), which limits and protects the gate-to-source voltage of the external mosfet. when the external mosfet fails to increase the source (or field coil pin) voltage to within a source short circuit threshold voltage (v tssc ) of the battery pin voltage (v tssc < [v bat - v source ] ), a shorted-source comparator c ss outputs a short circuit signal to a gate polling circuit. a shorted field coil to ground is an example of this fault condition. this gate polling circuit provides short gate polling pulses to the and4 gate to allow the ic to test for an unshorted condition without da maging the external mosfet. the polling duty cycle is 1.56%, or about a 158 s on pulse at a frequency of f msb /4, or 98.6 hz. when the source shorting condition is removed, comparator c ss provides a no- short signal to the gate polli ng circuitry, which provides a logic [1] to the and4 gate, which then operates normally. the and4 gate is also driven by the no load dump ( ld ) line from the overvoltage detector circuitry. thus during a load dump system overvolta ge condition, a logic [0] is provided to the and4 gate from the overvoltage detector circuit and all gate drive is terminated. a flyback diode mr850 is externally provided to limit the negative source voltage on th e field pin (and the source pin) caused by a turn-off transition of the field current. the forward current through this diode is approximately the peak field current prior to field current turn off. fault lamp indicator ? drive and protection the fault indicator lamp is driven by an internal n-channel mosfet lamp driver, which co ntrols the lamp current. the lamp is coupled between the ignition switch and the lamp drain pin of the lamp driver. the lamp gate of the lamp driver is driven by the lamp driver circuitry or from an external lamp gate pin. inputs to the lamp driver circuitry are from an output of an and2 gate, an output of a thermal limit circuit, and an output of a current limit circuit. by applying an external lamp gate override voltage (v go ) to the lamp gate pin (5), the lamp drain current will increase, providing lamp current independent of the la mp driver logic state. when the lamp driver circuity is forcing the lamp driver off, the lamp gate pin resistance to ground will be about 4.6 k ? . the source of the lamp driver is coupled to ground through an internal current sense resistor r s . when the lamp is on, the lamp drain on voltage (v d(sat) ) is the lamp drain-to-ground voltage measured at 400 ma of lamp drain current. normally, current flows through the lamp driver (and lamp), indicating a fault when the output of the and2 gate is a logic [1]. assuming the lamp is not shorted, is not being current limited, is not in the thermal shut down mode, and the system is not in a load dump mode, the lamp on current is controlled by the output of t he or2 gate. the output of the or2 gate is a logic [1] and the lamp will normally be on when the uv (undervoltage) line and the f2 output line are both a logic [1] state, indicating an undervoltage condition when frequency f ph > f 2 . the output of the or2 gate is also a logic [1] when the output of the ov (overvoltage) line is a logic [1], indicating an overvoltage condition, or the output of the f1 line is also a logic [1], indicating a loss of phase signal (f ph < f 1 ) due to a broken phase wire, broken or slipping belt, or otherwise failed alternator or open field circuit. when the lamp current exceeds a lamp drain short circuit current (i dsc ), the voltage across resistor rs will exceed a current limit threshold voltage associated with the current limit circuitry. as a result, a sign al is sent to the lamp driver
analog integrated circuit device data freescale semiconductor 15 33099 typical applications circuitry to limit the lamp drive and regulates the lamp current to current i dsc . when the power dissipation of the lamp driver causes the temperat ure of the lamp driver to exceed a thermal shut-down te mperature limit (t lim ), a temperature sensing diode (d tl ) causes the thermal limit circuitry to send a signal to the lamp driver circuitry to limit the lamp drive current and reduce the power dissipation and resulting device temperature. when the lamp driver is on, but the lamp drain pin voltage is not below the bat pin voltage v bat by at least a lamp drain short circuit threshold voltage (v tdsc ) or ([v bat - v drain ] < v tdsc ), comparator c ds will output a lamp short circuit signal to the drain polling circuit to indicate a lamp shorted condition. the drain polling circuit provides a low duty cycle polling output to th e input of the and2 gate to poll the lamp driver on, continuously testing for a lamp short without damaging the lamp driver. the polling duty cycle is 1.56%, (or about a 158 s on pulse) at a frequency of f msb /4, or 98.6 hz. after the lamp s hort has been removed, the comparator c ds outputs a lamp not-s horted signal to the drain polling circuitry, which provides a logic [1] to the and2 gate, which then operates normally. lamp polling is also present when the lamp is on. in this case, lamp polling turns off the lamp for a short period of time with the lamp being on for the remainder of the time. in this case the lamp on duty cycle is 98.44% (or off for 158 s) at a frequency of f msb /4, or 98.6 hz. this causes the lamp voltage on the lamp drain pin to be greater than ignition threshold voltage v tign for at least 158 s of a 10.1 ms period. during the lamp on mo de, the ignition turn off delay of the ignition delay circui t is greater then the 10.1 ms period. as a result, the regulator biasing remains on even when the ign pin is coupled to the lamp drain pin and the lamp drain voltage is less than voltage v tig n most of the time when the lamp is on. the lamp driver is also protected from load dump, since during load dump, the ld signal is a logic [0], preventing the and2 gate from activating the lamp driver. in addition, a drain-to-gate clamp device z2 limits the drain-to-gate clamping voltage (v dg ) to about 40 v typically. undervoltage, overvo ltage, and load dump protection an undervoltage, overvoltage and load dump condition is sensed by the regulator to generate fault indications and to protect the regulator and associated external devices. as previously discussed, a load dump signal during load dump will prevent gate drive to the external mosfet and prevent gate drive to the lamp driver. thus the external and internal mosfets will turn off duri ng a system load dump. as previously discussed, the undervoltage and overvoltage signals are also provided for fault indications. the undervoltage signal is provided on the uv line by an undervoltage comparator c uv having a voltage reference of 1.25 v and a resistor divider voltage transfer of 1.26 from the fb output to comparator c uv input. when voltage v fb on the fb output becomes less than 1.52 v, the voltage at input to comparator c uv becomes less than 1.25 v, causing comparator c uv to output an undervoltage uv signal. because voltage v fb is ideally voltage v rs (or voltage v ls ), and the ratio of v r / v rs (or v l / v ls ) is 7.45, the uv signal will occur when the system voltage at the remote input (or local input) is less than an underv oltage threshold voltage (v tuv ), or 11.35 v. however, gate and1 ensures that frequency f ph must be greater than f 2 before an undervoltage fault is indicated by the lamp. the load dump and overvoltage detection also utilizes similar resistor dividers and voltage comparators in an overvoltage detect circuitry where all comparators are referenced to voltage v ref , or about 2.0 v. when voltage v fb on the fb output is greater than 2.58 v, or 1.29 v ref (v fb / v ref = 1.29), an output load dump signal of a logic [0] is generated on the ld line. thus during load dump, voltage v rs (or v local ) will be about 2.58 v, and the actual load dump threshold voltage (v tld ) will be about 19.25 v, or 1.3 v set . when voltage v fb on the fb output is greater than 1.117 v ref (v fb / v ref = 1.117), an output overvoltage signal is generated on the ov line. thus voltage v rs (or v l ) will be about 2.235 v, and the actual overvoltage threshold voltage (v tov ) will be about 16.65 v, or 1.125 v set . the regulator also indicates an overvoltage condition on the system during the remote fault condition when the remote wire resistance increases to a finite value and the system voltage is being regulated by secondary regulation at v set2 . when a load dump occurs during secondary regulation, the load dump threshold increases to 1.3 v set2 , or about 24 v.
analog integrated circuit device data 16 freescale semiconductor 33099 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. dw suffix eg suffix (pb-free) 16-pin plastic package 98asb42567b issue f
analog integrated circuit device data freescale semiconductor 17 33099 revision history revision history revision date description of changes 5.0 6/2006 ? added revision history page ? converted to freescale format ? update to prevailing form and style 6.0 1/2007 ? updated the data sheet to the current form and style ? added mcz33099eg/r2 and mcz33099ceg/r2 to the ordering information block. ? removed peak package reflow temperature during reflow (solder reflow) parameter from maximum ratings on page 4 . ? added notes to maximum ratings on page 4
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